1. Technical Field
The present invention relates to a memory system and, more particularly, to a memory system and a control method of the same which can remove a timing skew between a memory controller and each of the memories mounted on memory modules.
2. Discussion of the Related Art
A conventional memory system includes a memory controller and a memory module. Each of the memory modules includes a plurality of memories. The memory controller receives/outputs data from/to each of the plurality of memories of the memory module. A command signal is commonly applied to the plurality of memories.
In conventional memory systems, a length of time that a memory controller receives/outputs data from/to each of a plurality of memories is identical, but a length of time that a command signal is applied to a plurality of memories varies from memory to memory. That is, the time that a command signal from the memory controller reaches each of the plurality of memories is different, whereas the time that data from the memory controller reaches each of a plurality of memories is identical.
Therefore, in conventional memory systems, data cannot be accurately written onto each of the plurality of memories from the memory controller, nor can data read from each of the plurality of memories be simultaneously inputted to the memory controller.
A method is suggested that each of the memory modules has one buffer circuit having a function for controlling a timing skew between a command signal and data. However, this method increases the cost of manufacture because each of the memory modules has to include a buffer circuit.
FIG. 1 is a block diagram illustrating a conventional memory system. The memory system of FIG. 1 includes a memory module 100 and a memory controller 200. The memory module 100 includes 8 memories 10-1 to 10-8.
In FIG. 1, reference numerals 22-1 to 22-8 represent data lines between the memory controller 200 and the respective memories 10-1 to 10-8, and reference numerals 20 and 20-1 to 20-8 represent command signal lines between the memory controller 200 and the respective memories 10-1 to 10-8.
As shown in FIG. 1, data is transmitted through the data lines 22-1 to 22-8 between the memory controller 200 and the respective memories 10-1 to 10-8, and a command signal is transmitted through the command signal lines 20 and 20-1 to 20-8 from the memory controller 200 to the memories 10-1 to 10-8.
The memory controller 200 applies a command signal and a write data to the memories 10-1 to 10-8 and receives a read data outputted from the memories 10-1 to 10-8. The memories 10-1 to 10-8 store a write data in response to the command signal sent from the memory controller 200 and output the read data to the memory controller 200.
In the memory system of FIG. 1, read and write data are transmitted between the memory controller 200 and the memories 10-1 to 10-8 at the same time, but the time that command signals reach the respective memories 10-1 to 10-8 is different. This is because the load of the signal line increases as the memories are located further away from the memories 10-4 and 10-5, thus the time that a command signal reaches these memories is delayed. As a consequence, the command signal reaches the memories 10-4 and 10-5 the earliest and reaches the memories 10-1 and 10-8 the latest.
Therefore, in the memory system of FIG. 1, during a write and read operation, data cannot be written accurately because the time that each command signal reaches each of the memories 10-1 to 10-8 is different, and the time that data being read from the memories 10-1 to 10-8 to the memory controller 200 is different as well.
For the foregoing reason, the conventional memory system cannot perform a stable data transmission during a write and read operation.